I-IP 2006 - Call for Papers

CALL FOR PAPERS

Scope -- Author Information -- Committees

Scope

The higher level of manufacturing susceptibility and field reliability in today’s SoC require enhanced detection, diagnosis and yield optimization solutions. These solutions necessitate incorporating on-chip infrastructure IP blocks, in addition to the functionality of the SoC. The Infrastructure IP leverages the manufacturing knowledge and feeds back the information into the design phase. This workshop analyzes this key trend and gives the chance to describe a range of infrastructure IP for today's System-on-Chip (SoC) designs. This includes infrastructure IP for test, diagnosis, timing measurement, debugging, test, repair, and fault tolerance.

Areas of Interest include but are not limited to

Embedded diagnosis IP
Design for Manufacturability
Built-in Repair Analysis and Built-in Self-Repair
Yield enhancement IP
Built-in monitors and embedded measurement functions
Embedded Test solutions (BIST)
On-line error detection and correction blocks
Transient error protection hardware
Process monitoring IP
Silicon debug infrastructure

Author Information

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To present at the Workshop, authors are invited to submit paper proposals. The proposals may be extended abstracts (1,000 words) or full papers. Each submission should include: title, full name and affiliation of all authors, an abstract of 50 words, and keywords. Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address.
Submit a copy of your paper proposal by Postscript, or PDF, via E-mail. Proposals for panel discussions are also invited. Submissions are due no later than March 11, 2006.

Submit your paper proposal to:

- Dimitris Gizopoulos, Piraeus U, dgizop@unipi.gr, Tel: +30-210-414-2372

Authors will be notified of the disposition of their papers by March 30, 2006.

Authors of accepted papers may submit an illustrated text by April 10, 2006 for inclusion in the Digest of Papers, which will be provided to the attendees.

For general information contact:

Yervant Zorian
Virage Logic Corp
Tel: +1-510-360-8035
Fax: +1-510-360-8078
E-mail: yzorian@computer.org

Committees

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General Chair
Y. Zorian, Virage Logic

Vice-General Chair
A. Ivanov, U British Columbia

Program Chair
D. Gizopoulos, U Piraeus

Finance
R. Aitken, Artisan

Publicity
A. Khoche, Agilent

Publication Chair
P. Prinetto, Pol. di Torino

Panels Chair
H-J. Wunderlich, U of Stuttgart

Program Committee to include

M. Abadir, Freescale
M. Abramovici, Dafca
D. Appello, ST Microelectronics
S. Bhawmik, Conexant
D.Burek, Magma
W-T. Cheng, Mentor Graphics
K. Darbinyan, Virage Logic
J. Doege, DA-Test
A. Gattiker, IBM
S.K. Goel, Philips
B. Kaminska, Pultronics
H. Manhaeve, Qstar
H. Masuda, STARC
E.J. McCluskey, Stanford U
T. McLaurin, ARM
C. Metra, U of Bologna
M. Mowji LTX
M. Nicolaidis, TIMA
A. Orailoglu, UC San Diego
J.M. Portal, U of Marseille
J. Reynick, eSilicon
M. Ricchetti, ATI
M. Sonza Reorda, Poli. di Torino
S. Tabatabaei, Virage Logic Corp
B. Vermeulen, Philips
H-J. Wunderlich, U of Stuttgart
G. Yeric, Synopsys

For more information, visit us on the web at: http://www.unipi.gr/iip/

The 4th IEEE International Workshop on Infrastructure IP (I-IP 2006) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).